The present invention relates to a variable-frequency pulse generator capable of generating a pulse of the desired frequency.
A conventional variable-frequency pulse generator will be explained below. A conventional variable-frequency pulse generator has been disclosed in Japanese Patent Application No. 11-220364. FIG. 12 shows a configuration of a variable-frequency pulse generator disclosed in the above publication.
In FIG. 12, the reference symbol 100 denotes a conventional variable-frequency pulse generation circuit, 101 denotes a bit inverter which inverts a first reference value D1, 102 denotes a data selector which selects either one of the output of the inverter 101 and a pulse number set value Ps, 103 denotes a digital adder which adds the output xcex81 of a first data holding circuit described later and the output of the data selector 102, and 104 denotes the first data holding circuit which latches the output xcex82 of the digital adder 103 at the timing T2 of a reference clock fb. The reference symbol 105 denotes a first data comparator which compares the output xcex81 of the first data holding circuit 104 and the first reference value D1, and 106 denotes a second data comparator which compares the output xcex81 of the first data holding circuit 104 and a second reference value D2. The reference symbol 107 denotes a pulse generation circuit which judges the output level (High or Low) based on the two comparison results, 108 denotes a second data holding circuit which latches the output fd of the pulse generation circuit 107 at the timing T3 of the reference clock fb and outputs a pulse train fout, and 109 denotes an overflow prevention circuit which outputs the overflow prevention signal fob synchronous with the reference clock fb based on the comparison result of the first data comparator 105.
The control clock frequency fc is [fb/4]. The first reference value D1 is [fcxc3x97n], and the second reference value D2 is [(fc/2)xc3x97n]. The pulse number set value per n seconds Ps is [Vpxc3x97n], and the value thereof can be set for 1 unit in the range of [0xe2x89xa6Psxe2x89xa6{(fc/2)xc3x97n}]. n denotes the maximum cycle of the output pulse, and Vp denotes a speed set value.
The operation of the conventional variable-frequency pulse generator will now be explained. The inverter 101 outputs a bit inversion value of the reference value D1 in the 26-bit notation. When the S terminal is 0 (xcex81xe2x89xa6D1), the data selector 102 outputs the pulse number set value Ps (26-bit notation) of a terminal A to a terminal Y, and when the S terminal is 1 (xcex81 greater than D1), the data selector 102 outputs the bit inversion value of the reference value D1 of a terminal B to the terminal Y.
When a CIN terminal is 0 (xcex81xe2x89xa6D1), the digital adder 103 adds the pulse number set value Ps output from the data selector 102 and the output xcex81 of the first data holding circuit 104, and when the CIN terminal is 1 (xcex81 greater than D1), the digital adder 103 adds xe2x88x92(fcxc3x97n), being the sum of the output of the data selector 102 and CIN=1, and the output xcex81 of the first data holding circuit 104, and outputs the addition result xcex82 (26-bit notation) for each case. The first data holding circuit 104 latches the addition result xcex82 at the timing T2 of the reference clock fb and the overflow prevention signal fob, and outputs data xcex81 (26-bit notation).
The first data comparator 105 compares the output xcex81 of the first data holding circuit 104 and the first reference value D1, and when xcex81 greater than D1, outputs 1 as the overflow signal. The second data comparator 106 compares the output xcex81 of the first data holding circuit 104 and the second reference value D2. The pulse generation circuit 107 judges the both comparison results, and for example, when the comparison results by the both comparators are 0xe2x89xa6xcex82 less than D2 (=(fc/2)xc3x97n), outputs 0 as the judgment result fd, and when D2xe2x89xa6xcex82 less than D1 (=fcxc3x97n), outputs 1, and when D1xe2x89xa6xcex82, outputs 0. The second data holding circuit 108 latches the judgment result fd at the timing T3 of the reference clock fb, and outputs a pulse train fout.
The overflow prevention circuit 109 receives the overflow signal output from the first data comparator 105 at the timing T4 of the reference clock fb, and outputs an overflow prevention signal fob.
FIG. 13 is a timing chart which shows the operation of the conventional variable-frequency pulse generator. At first, the speed change timing xcex94t changes at a period synchronous with the timing T1 of the reference clock fb and the speed change timing, and acceleration and deceleration speed is latched at the timing T1 of the reference clock fb. This operation is executed by the part other than the configuration shown in FIG. 12.
The first data holding circuit 104 latches the output xcex82 of the digital adder 103 at the timing T2 of the reference clock fb. The second data holding circuit 108 then latches the output fd of the pulse generation circuit 107 at the timing T3 of the reference clock fb, and outputs the pulse train fout.
The overflow prevention circuit 109 performs overflow prevention processing with respect to the output xcex81 of the first data holding circuit 104, at the timing T4 of the reference clock fb. That is, when overflow occurs (xcex81 greater than D1), and fb=(High), the overflow prevention circuit 109 outputs the overflow prevention signal fob (=High).
However, in the conventional variable-frequency pulse generator, control for four cycles of the reference clock is necessary during the period of from the speed setting until the overflow prevention processing is completed, that is, during 1 cycle of output control of the pulse train fout. Therefore, the reference clock of a frequency of 8 times or more is required in order to actually obtain the pulse train of a desired frequency (see FIG. 13). As a result, in the conventional variable-frequency pulse generator, with the speed-up of the reference clock, there is caused a problem in that the noise, power consumption and heat generation of the whole apparatus considerably increase.
It is an object of the present invention to provide a variable-frequency pulse generator capable of reducing the noise, power consumption and heat generation compared to the conventional apparatus.
The variable-frequency pulse generator according to the present invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit (corresponding to an inverter 11 in the embodiment described later) which inverts a first reference value regulated by the reference clock, a selection unit (corresponding to a data selector 12) which selects the first reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit (corresponding to a first data holding circuit 14) which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of an overflow prevention signal, an addition unit (corresponding to a digital adder 13) which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit (corresponding to a first data comparator 15) which compares the value obtained by the addition unit as a result of addition and the first reference value, a second comparison unit (corresponding to a second data comparator 16) which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value, a judgment unit (corresponding to a pulse generation circuit 17) which judges whether a condition xe2x80x9c0xe2x89xa6addition result less than second reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9csecond reference valuexe2x89xa6addition result less than first reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9cfirst reference valuexe2x89xa6addition resultxe2x80x9d is satisfied, and outputs a specified signal corresponding to a result of the judgment, a pulse train output unit (corresponding to a second data holding circuit 18) which latches the specified signal at a predetermined timing of the second cycle of the reference clock, and outputs a pulse train of a desired frequency, a third comparison unit (corresponding to a third data comparator 19) which compares the data latched by the data holding unit and the first reference value, and when a condition xe2x80x9clatched dataxe2x89xa7first reference valuexe2x80x9d is satisfied, judges that the overflow has occurred, and an overflow prevention unit (corresponding to an overflow prevention circuit 20) which outputs the overflow prevention signal at a predetermined timing of the first cycle of the reference clock, when the third comparison unit has judged that the overflow has occurred.
The variable-frequency pulse generator according to the next invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an addition unit (corresponding to a digital adder 21) which adds a predetermined value, which changes depending on a set speed, and data latched at a predetermined timing of the second cycle of the reference clock, a subtraction unit (corresponding to a digital subtracter 22) which subtracts a first reference value regulated by the reference clock from the value obtained by the addition unit as a result of addition, a first comparison unit (corresponding to a first data comparator 25) which compares the value obtained by the addition unit as a result of addition and the first reference value, and when a condition xe2x80x9caddition resultxe2x89xa7first reference valuexe2x80x9d is satisfied, judges that an overflow has occurred, a second comparison unit (corresponding to a second data comparator 26) which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value, a selection unit (corresponding to a data selector 23) which selects the value obtained by the subtraction unit as a result of subtraction when the overflow has occurred, and in any other event selects the value obtained by the addition unit as a result of addition, a data holding unit (corresponding to a first data holding circuit 24) which latches the value selected by the selection unit at a predetermined timing of the second cycle of the reference clock, a judgment unit (corresponding to a pulse generation circuit 27) which judges based on each the results of comparisons in the first comparison unit and the second comparison unit, whether a condition xe2x80x9c0xe2x89xa6addition result less than second reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9csecond reference valuexe2x89xa6addition result less than first reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9cfirst reference valuexe2x89xa6addition resultxe2x80x9d is satisfied, and outputs a specified signal according to a result of the judgment, and a pulse train output unit (corresponding to a second data holding circuit 28) which latches the specified signal at a predetermined timing of the second cycle of the reference clock, and outputs a pulse train of a desired frequency.
The variable-frequency pulse generator according to the next invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit which inverts a reference value regulated by the reference clock, a selection unit which selects the reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of an overflow prevention signal, an addition unit which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit which compares the value obtained by the addition unit as a result of addition and the reference value, a judgment unit (corresponding to a pulse generation circuit 17c) which judges whether a condition xe2x80x9cthe overflow frequency is an even numberxe2x80x9d and xe2x80x9c0xe2x89xa6addition result less than reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9cthe overflow frequency is an even numberxe2x80x9d and xe2x80x9creference valuexe2x89xa6addition resultxe2x80x9d is satisfied, or whether conditions xe2x80x9cthe overflow frequency is an odd numberxe2x80x9d and xe2x80x9c0xe2x89xa6addition result less than reference valuexe2x80x9d are satisfied, or whether conditions xe2x80x9cthe overflow frequency is an odd numberxe2x80x9d and xe2x80x9creference valuexe2x89xa6addition resultxe2x80x9d are satisfied, and outputs a specified signal corresponding to a result of the judgment, a pulse train output unit which latches the specified signal at a predetermined timing of the second cycle of the reference clock, and outputs a pulse train of a desired frequency, a second comparison unit which compares the data latched by the data holding unit and the reference value, and when a condition xe2x80x9clatched dataxe2x89xa7reference valuexe2x80x9d is satisfied, judges that the overflow has occurred, and an overflow prevention unit which outputs the overflow prevention signal at a predetermined timing of the first cycle of the reference clock, when the second comparison unit has judged that the overflow has occurred.
The variable-frequency pulse generator according to the next invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit which inverts a first reference value regulated by the reference clock, a selection unit which selects the first reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of the overflow prevention signal, an addition unit which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit which compares the value obtained by the addition unit as a result of addition and the first reference value, a second comparison unit which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value, a judgment unit which judges whether a condition xe2x80x9c0xe2x89xa6addition result less than second reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9csecond reference valuexe2x89xa6addition result less than first reference valuexe2x80x9d is satisfied, or whether a condition xe2x80x9cfirst reference valuexe2x89xa6addition result less than (second reference valuexc3x973)xe2x80x9d is satisfied, or whether a condition xe2x80x9c(second reference valuexc3x973)xe2x89xa6addition resultxe2x80x9d is satisfied, and outputs a specified signal corresponding to a result of the judgment, a pulse train output unit which latches the specified signal at a predetermined timing of the second cycle of the reference clock, and outputs a pulse train of a desired frequency, a third comparison unit (corresponding to a third data comparator 19d) which compares the data latched by the data holding unit and the first reference value, and when a condition xe2x80x9clatched data greater than first reference valuexe2x80x9d is satisfied, judges that the overflow has occurred, and an overflow prevention unit which outputs the overflow prevention signal at a predetermined timing of the first cycle of the reference clock, when the third comparison unit has judged that the overflow has occurred.